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FTW
REG
PHASE
ACCUM.
COSINE
LOOK
UP
TABLE
DIGITAL TO
ANALOG
CONVERTER
CONTROL REGISTER
REFERENCE CLOCK
LOW
PASS
FILTER
32
BITS
14
BITS
(a)
10
BITS
(b)
NUMERICALLY CONTROLLED OSCILLATOR
32 Bit FTW
5 Bit Phase
EXAMPLE DDS (AD9850)
40-BIT SERIAL DATA WORD (FTW & CTL)
ANALOG
OUT
FIGURE 1. INTERNAL DDS DIAGRAM
(c)
(a)
(b)
(c) (poor)
(a) Phase Accumulator Values
per Clock Pulse
00
20
40
60
80
A0
C0
E0
0 Deg.
or 360 Deg.
00 00 00 00
0x 20 00 00 00
0x 40 00 00 00
0x 60 00 00 00
0x 80 00 00 00
0x A0 00 00 00
0x C0 00 00 00
0x E0 00 00 00
20
00
40
60
80
A0
C0
E0
NOTE: These are the Most Significant byte of FTW only
FIGURE 2. Phase Accumulator Values and FTW
Versus Phase angle of full cycle
(b). FTW values for various phase angles